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| rev.2.01, nov.29.2 016, page 1 of 7 hat2200r silicon n channel power mos fet power switching rej03g0232-0201z rev.2.01 nov.29.2016 features ? capable of 8 v gate drive ? low drive current ? high density mounting ? low on-resistance r ds(on) = 22 m ? typ. (at v gs = 10 v) outline sop-8 1 2 3 4 5 6 7 8 1, 2, 3 source 4 gate 5, 6, 7, 8 drain g d sss d dd 4 1 23 56 7 8
hat2200r rev.2.01, nov.29.2 016, page 2 of 7 absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 100 v gate to source voltage v gss 20 v drain current i d 8a drain peak current i d(pulse) note1 64 a body-drain diode reverse drain current i dr 8a avalanche current i ap note 2 8a avalanche energy e ar note 2 6.4 mj channel dissipation pch note3 2.5 w channel to ambient thermal impedance ch-a note3 50 c/w channel temperature tch 150 c storage temperature tstg C55 to +150 c notes: 1. pw 10 s, duty cycle 1% 2. value at tch = 25c, rg 50 ? 3. when using the glass epoxy boar d (fr4 40 x 40 x 1.6 mm), pw 10s electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 100 v i d = 10 ma, v gs = 0 gate to source leak current i gss 0.1 av gs = 20 v, v ds = 0 zero gate voltage drain current i dss 1 av ds = 100 v, v gs = 0 gate to source cutoff voltage v gs(off) 3.5 5.0 v v ds = 10 v, i d = 1 ma static drain to source on state r ds(on) 2228m ? i d = 4 a, v gs = 10 v note4 resistance r ds(on) 2333m ? i d = 4 a, v gs = 8 v note4 forward transfer admittance |y fs |8 14s i d = 4 a, v ds = 10 v note4 input capacitance ciss 2300 pf v ds = 10 v output capacitance coss 280 pf v gs = 0 reverse transfer capacitance crss 90 pf f = 1 mhz gate resistance rg 1.3 ? total gate charge qg 32 nc v dd = 50 v gate to source charge qgs 12 nc v gs = 10 v gate to drain charge qgd 8 nc i d = 8 a turn-on delay time t d(on) 16nsv gs = 10 v, i d = 4 a rise time t r 4 nsv dd ? 30 v turn-off delay time t d(off) 32nsr l = 7.5 ? fall time t f 4.5 ns rg = 4.7 ? bodyCdrain diode forward voltage v df 0.79 1.03 v if = 8 a, v gs = 0 note4 bodyCdrain diode reve rse recovery time t rr 45 ns if = 8 a, v gs = 0 dif/ dt = 100 a/ s notes: 4. pulse test hat2200r rev.2.01, nov.29.2 016, page 3 of 7 main characteristics channel dissipation pch (w) ambient temperature ta (c) power vs. temperature derating 4.0 3.0 2.0 1.0 0 50 100 150 200 test condition : when using the glass epoxy board (fr4 40x40x1.6 mm), pw < 10 s drain to source voltage v ds (v) drain current i d (a) maximum safe operation area note 5 : when using the glass epoxy board (fr4 40x40x1.6 mm) 10 1 0.1 0.01 0.001 0.1 0.3 1 3 10 30 300 1000 100 100 ta = 25c 1 shot pulse pw = 10 ms 10 s 100 s operation in this area is limited by r ds(on) dc operation (pw 10 s) note 5 1 ms drain to source voltage v ds (v) drain current i d (a) typical output characteristics 20 16 12 8 4 0 2468 10 v gs = 5.4 v 10 v 6 v pulse test 5.8 v gate to source voltage v gs (v) drain current i d (a) typical transfer characteristics 20 16 12 8 4 0 2468 10 tc = 75c 25c ?25c v ds = 10 v pulse test gate to source voltage v gs (v) drain to source voltage v ds(on) (mv) drain to source saturation voltage vs. gate to source voltage 250 200 150 100 50 0 5101520 pulse test i d = 5 a 1 a 2 a drain current i d (a) drain to source on state resistance r ds(on) (m?) static drain to source on state resistance vs. drain current 20 10 2 5 1 11 0 100 100 50 v gs = 8 v 10 v pulse test 5.6 v hat2200r rev.2.01, nov.29.2 016, page 4 of 7 case temperature tc (c) static drain to source on state resistance r ds(on) (m?) static drain to source on state resistance vs. temperature 50 40 30 20 10 -25 0 5025 10075 125 150 2 1 a, 2 a, 5 a i d = 1 a, 2 a, 5 a v gs = 8 v 10 v pulse test forward transfer admittance |yfs| (s) drain current i d (a) forward transfer admittance vs. drain current 330 0.1 1 10 100 0.3 10 100 1 tc = ?25c v ds = 10 v pulse test 75c 25c reverse drain current i dr (a) reverse recovery time trr (ns) body?drain diode reverse recovery time 1 10 100 100 20 50 10 0.1 di/dt = 100 a/ s v gs = 0, ta = 25c capacitance c (pf) drain to source voltage v ds (v) typical capacitance vs. drain to source voltage 0102030 50 40 10000 3000 1000 300 100 30 10 ciss coss crss v gs = 0 f = 1 mhz gate charge qg (nc) drain to source voltage v ds (v) gate to source voltage v gs (v) dynamic input characteristics 250 200 150 100 50 0 20 16 12 8 4 10 20 30 40 50 0 i d = 8 a v gs v ds v ds = 100 v 50 v 25 v v ds = 100 v 50 v 25 v drain current i d (a) switching time t (ns) switching characteristics 100 10 1 1 10 100 0.1 1000 v gs = 10 v, v ds = 30 v rg = 4.7, duty < 1 % t d(on) t d(off) t r t f hat2200r rev.2.01, nov.29.2 016, page 5 of 7 source to drain voltage v sdf (v) reverse drain current i f (a) 20 16 12 8 4 0 0.4 0.8 1.2 1.6 2.0 reverse drain current vs. source to drain voltage pulse test v gs = 0 v, ?5 v 10 v 10 8 6 4 2 25 50 75 100 125 150 0 channel temperature tch (c) repetitive avalanche energy e (mj) ar maximum avalanche energy vs. channel temperature derating i ap = 8 a v dd = 50 v duty < 0.1 % rg > 50 ? pulse width pw (s) normalized transient thermal impedance vs. pulse width normalized transient thermal impedance s (t) 10 100 1 m 10 m 100 m 1 10 100 1000 10000 10 1 0.1 0.01 0.001 0.0001 d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot pulse dm p pw t d = pw t ch - f(t) = s (t) x ch - f ch - f = 83.3c/w, ta = 25c when using the glass epoxy board (fr4 40 x 40 x 1.6 mm) hat2200r rev.2.01, nov.29.2 016, page 6 of 7 d. u. t rg i monitor ap v monitor ds v dd 50 ? vin 15 v 0 i d v ds i ap v (br)dss l v dd e ar = l i ap 2 2 1 v v - v dss dss dd avalanche test circuit avalanche waveform vin monitor d.u.t. vin 10 v r l v = 30 v ds tr td(on) vin 90% 90% 10% 10% vout td(off) vout monitor 90% 10% t f switching time test circuit switching time waveform rg hat2200r preliminary rev.2.01, nov.29.2016, page 7 of 7 package dimensions p-sop8-3.95 4.9-1.27 0.085g mass[typ.] fp-8dav prsp0008dd-d renesas code jeita package code previous code a 8 5 1 4 f b p c detail f terminal cross section 1.27 1.08 0.40 l 1 0.60 0.25 x 0.46 0.40 0.34 0.10 b p b 1 c 1 0.250.200.15 max nom min dimension in millimeters symbol reference 5.3 4.90 d 3.95 e 0.14 a 2 6.206.105.80 0.25 1.75 a 0.75 z l 8 0 c 1.27 e 0.1 y h e a 1 d * 1 * 2 e h e * 3 x m b p e z (ni/pd/au plating) 2. 1. dimensions "*1(nom)" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark a 1 l 1 l detail f y package name sop-8 ordering information orderable part number quan tity shipping container hat2200r-el-e 2500 pcs taping note: for some grades, production may be terminated. please contact the renesas sales office to check the state of production before ordering the product. general precautions in the handling of power mosfet and igbt products the following usage notes are applicable to general purpose power mosfet and igbt products from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. derating continuous heavy condition (e.g. high te mperature/voltage/current or high vari ation of temperature) may affect a reliability even if it are within the absolute maximum ra tings. please consider derating condition for appropriate reliability in reference renesas semiconductor reliability handbook (recommendation for handling and usage of semiconductor devices) and individual reliability data. 2. quality grade ? the quality grade of this product is ?standard?. ? if you plan to use this product to ?high quality? application, please inform to renesas. ? fail safe system is necessary to prevent malfunction even if this product is broken. ? 2016 renesas electronics corporation. all rights reserved. colophon 5.0 descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics do es not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property right s of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. 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?cva?e3,o??+kd%=e, a? -.??+^?b* d ?2?y ,o? a+^?>+^m? ^a?=a?ac+^ b? ?c,o+kd%=e, a-.??b-8 >?cucy>/?+^ml1b?? +^@f&+kd%= e,l6bf ,o1??g?*?:^+k?c?1?cy1> ^= b? ?va?e3,o,oey0ac?*?:^+k?(sh?f >*<# e?| e?*?:^+k??caf?g3 e. b%,o>+^m b? ?cva?e3,o,okob%lf?%e6bf ,o1??g?*?:^+k?c? 1?cy1> /? +^ b? ?c,o*?:^+k?y l? e6bfvf,o? y>?pl !?6b?(?1b??,oi_=(~ yl? .ay y,o>?p?*?:^+k?c?1?cy1> b? ?va?e3,o??c?p/*?:^+k?l? e v ?,oi_=(~ yl? .ay y?01? d/p=u/pl?1?e,oa? % ? y> +^mc *o=$o=cll6;? ?eg <l?g fm?# +^*?:^+k?,o1?y >/?+^ml1b?? @f& *o=$o=cll? ?em?# +^*?:^+k?y ,o>?p6bf ,o1??g?*?:^+k? c?1?cy1> *?:^+k?y o?c^h14y<pz`14y?? =14y? a?qc^h14y?>"0*?:^+k?y ,ot9?+^fj } ?y ,oc^h14y??av/p? =14y? a1 p=?a?==fpa?a?==#?b a#?ha?==? ba?==+^+k ?= p ?-=`e+k?a?= p p ?e1> qc^h14y? fea?="3e?=&?e?=e8o1=fpyl315=lh&315=nolh(?5?315 ??a?=1> *?:^+k?y e+^?j `>? y+^? %73/e2+u 3fvf-*?76,oy l315 %73fvfedz,oy l315e+u 35*7>?5l315= c???,o>?51c?l6; %73fvfh]cxy?g,oy l315 n <yl315=?+^a?=1c> ^<"0*?:^+k?y +^? 0(e+^???+^m~.a?c^h14y>c<*?:^+k?y +^?c?0?a?a+^fj?l,o1?+^>/?+^ml1b?? <*?:^+k?y +^??a?a+^fj?l6bf ,o1??l?g?*?:^+k?c?1?cy1> +^ b? ?ca?e3,o*?:^+k?y ,? ^*?:^+k?=e,o99 *??(a e ^ 6]ner=+k$??+k 99 *=01t+k$?+k 99 *='#e?:(]=?>? ?, ? y (],o99 *?+^>/? ^@f&=e 99 *?l+^*?:^+k?y 6by+u,o{ll?g?*?:^+k?c?1?cy1> <3'l*?:^+k?6-*8*??q*?:^+k?y ,oc^h a %m?]?| e? ?2?y ??8 d,o-?(]??6e,o{l +u)? ^ ?+^ ?,ap +u{l1>!?l?*?:^+k?y } `f>?lhe?:a?a> vb-gy ???f??*?:^+k?y ^ +u{l6bfvf&?& ,28*ed{=zl?,o{>?f>?e.,??a?a ;"|cl???a?a=lh&?yl {lnolh1=f8?,o67 l :*<l? f8?,o1>+g?l??/? pe, ?)"f>?af?vb-+^m8 >?/ 64ty l315f>???af> ??)?1?m?,ob 4????"0*?:^+k?y ,o)?12?]1?b-d*?:^+k?,o:[pg l 6?31>+^*?:^+k?y ,?b-f??/1l(?c^,o+^l ahf>?1*<,ov ?-.# # ? ;"|cl?? e!]- rohs =f>/? +^m `f??-.# # ?6b28*,o?l?g?*?:^+k?c?1?cy1> c %<*?:^+k?y a? e+^?l6;?? b 3?l#-l-.,o# # ?v/!?+uy=+^ k6 d,o1?y l315c>?c %< b? ?ca?e3,o*?:^+k?y l? e+^?d?+^l6;?+^fj ??,o 1?-$,o?]? w vz]!? ?,o6 1> ^< b? ?ca?e3,o*?:^+k?y l? ef>?0 ,??f??-.,o0 1l# # ????'?@f&# # ?v?e,o0a?f>?> g1b?? 5?1b??yl?a,o*?:^+k?y |?l a ?,?/?+^ml1b?? m?# +^*?:^+k?y 6bf ,o1??g?*?:^+k?c?1?cy1> ^~ `f*?:^+k??m?a %,o??a?c1??eg <l?g ee3lcl b? ?> ? / b? ?va?e3,ol*?:^+k?y ?1?+?l$?l6;+^m ?1?? +?l$?b- g*?:^+k?,o:[pg l tb> notice 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 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